1. Field of the Invention
The present invention relates to a multilevel interconnect structure for use in a semiconductor device and more particularly relates to a multilevel interconnect structure in which upper and lower level metal wirings are interconnected by means of a plug provided in a via hole formed in an interlayer insulating layer arranged between the upper and lower metal wirings, said plug forming a current path from which an undesired interface between different kinds of metals are removed so that a reliability of the semiconductor device is improved.
The present invention also relates to a method of manufacturing the above mentioned multilevel interconnect structure for use in a semiconductor device.
2. Related Art Statements
Heretofore, in an LSI having a design rule larger than about 1 .mu.m, a metal wiring pattern of a multilevel interconnect structure has been formed by selectively etching a single aluminum or aluminum alloy film into a desired pattern. Further, in order to form an interconnection between lower and upper metal wirings, an interlayer insulating film is formed on the lower metal wiring, a via hole is formed in the interlayer insulating film, and then a metal film is deposited in the via hole as well as on the interlayer insulating film. After that the metal film is selectively etched into a desired pattern to form the upper metal wiring.
In accordance with the progress in the miniaturization of the semiconductor device, the design rule of LSI has been made smaller than 1 .mu.m. Then, in the known multilevel interconnect structure metal formed in the manner mentioned above, the reliability of the device might be decreased due to the stressmigration. In order remove such a problem, there have been proposed several techniques. For instance, in K. Kato and S. Shimizu, Proceedings of ECS Symposia , Vol. 89-6, p. 26, 1989 (reference 1), there is described a method of manufacturing the multilevel interconnect structure, in which a metal wiring pattern is formed by selectively etching a stack of at least one aluminum alloy film and at least one high melting point metal alloy film such as TiW, TiN and MoSix. Further, H. Yamamoto, S. Fujii, T. Kakiuchi, K. Yano and T. Fujita reported in Technical Digest of International Electron Device Meeting, Washington D.C., December 6-9, p. 205, 1987 (reference 2) has proposed another known method of manufacturing the multilevel interconnect structure. In this known method, after an aluminum alloy film is shaped into a desired pattern, upper surface and side wall of the aluminum alloy film pattern are covered with a high melting point metal film such as W film. The multilevel interconnect structure formed by this known method has been proved to have a high reliability, and thus this technique has been considered to be essential for realizing LSI having the design rule smaller than about 0.8 .mu.m.
In the known methods which have been used for manufacturing multilevel interconnect structures for use in LSI having the design rule larger than about 1 .mu.m, it is difficult to obtain a good interconnection between the lower and upper metal wirings and thus the yield and reliability of the semiconductor device might be decreased. That is to say, the upper metal wiring is generally formed by the sputtering which has a poor step coverage, and therefore the thickness of the metal film deposited on the inner wall of the via hole is liable to be thin and the interconnection might be broken at this point.
In S. R. Wilson et al, Proceeding of the Seventh International IEEE VLSI Multilevel Interconnection Conference, p. 42, 1990 (reference 3), there is disclosed another known method of forming the multilevel interconnection structure, in which the via hole is formed to have a trapezoidal cross sectional configuration and the step coverage of an aluminum alloy film constituting the upper metal wiring is improved by controlling the substrate temperature during the deposition of the aluminum alloy. However, such a technique could not be practically applied to LSI having the design rule smaller than about 0.6 .mu.m.
In view of the above, for LSI having the design rule smaller than about 0.6 .mu.m, a method in which at first the via hole is filled with the metal plug to form a flat surface and then the upper metal film is formed on this flat surface has been considered to be a major method. In the above mentioned reference 3, there is described a known method, in which a plug is formed by selectively depositing tungsten in the via hole by means of a selective CVD method. Further, in C. A. Bollinger et al, Proceeding of the Seventh International IEEE VLSI Multilevel Interconnection Conference, p. 21, 1990 (reference 4), there is proposed another known method of forming the plug in the via hole. In this known method, a barrier metal film such as TiW film is deposited in the via hole as well as on the interlayer insulating film, a W film is formed on the whole surface of the TiW film, and then a portion of the W film on the interlayer insulating film is selectively removed.
FIG. 1 is a cross sectional view showing the known multilevel interconnect structure for use in LSI having the design rule smaller than about 0.6 .mu.m. On a silicon substrate 101 there is deposited an underlaying insulating film 102. A lower metal wiring 103 is consisting of an aluminum alloy film 103-2 and a TiW film 103-3 and an upper metal wiring 107 is consisting of an aluminum alloy film 107-1 and a TiW film 107-2. Such a multilevel interconnect structure has a sufficient reliability for use in LSI having the design rule smaller than 0.6 .mu.m. The lower and upper metal wirings 103 and 107 are physically and electrically isolated by an interlayer insulating film 104 and a via hole 105 is formed in the insulating film 104. In the via hole 105 there is formed a plug 108 made of tungsten. In this manner, the multilevel interconnection structure which could be effectively used for LSI having the design rule smaller than 0.6 .mu.m can be obtained.
FIGS. 2A to 2E are cross sectional views illustrating successive steps of a known method for manufacturing the known multilevel interconnection structure shown in FIG. 1.
As shown in FIG. 2A, on a silicon substrate 101 there has been formed an underlaying insulating film 102. On the insulating film 102 there is formed an aluminum alloy film 103-2 having a thickness of 300 to 800 nm by means of sputtering. On the aluminum alloy film 103-2 there is further formed a TiW film 103-3 having a thickness of 20 to 100 nm also by means of sputtering.
Next, as illustrated in FIG. 2B, a stack of the aluminum alloy film 103-2 and TiW film 103-3 is shaped into a desired pattern to form a lower metal wiring 103. Then, an interlayer insulating film 104 is formed on the lower metal wiring 103 as well as on the exposed underlaying insulating film 102. The interlayer insulating film 104 may be formed by a combination of a SiO.sub.2, film deposited by, for instance plasma CVD method and a spin-on-glass film (SOG film). Next, in the interlayer insulating film 104 there is formed a via hole 105 as depicted in FIG. 2C, and then CVD process is carried out in an atmosphere including, for instance WF6 and SiH4 to deposit a tungsten selectively in the via hole to form a tungsten plug 108 in the via hole 105. This condition is shown in FIG. 2D.
Finally an aluminum alloy film 107-1 having a thickness of 400 to 1000 nm is formed by, for instance sputtering and then a TiW film 107-2 having a thickness of 20 to 100 nm is formed also by sputtering. Then, a stack of the aluminum alloy film 107-1 and TiW film 107-2 is selectively etched in accordance with a given pattern to form an upper metal wiring 107 as shown in FIG. 2E.
In the known multilevel interconnect structure shown in FIG. 1, two interfaces between different kinds of metals are provided in a current path between the lower metal wiring 103 and the plug 108. That is to say, there are formed a first interface between the aluminum alloy film 103-2 and the TiW film 103-2, a second interface between the TiW film 103-3 and the tungsten plug 108, and a third interface between the tungsten plug 108 and the aluminum alloy film 107-1. The existence of these interfaces between different kinds of metals results in the deterioration in the electrical property of the multilevel interconnection. For example, the via contact resistance becomes higher than the case in which the interconnection is performed by the contacts between the same kinds of metal such as aluminum alloy-aluminum alloy. This has been described in the above mentioned reference 3.
The reliability of the via interconnection in the above explained known multilevel interconnect structure can be really improved due to the fact that the upper metal wiring 107 is formed by depositing the metal film on the flat surface which is realized by filling the via hole 105 with the metal of the plug 108, and therefore the breakage of the interconnection due to the decrease in the thickness of the upper wiring metal film on the side wall of the via hole can be prevented as compared with the case in which the plug is not used. This has been described in F. Matsuoka et al, IEEE Transactions on Electron Devices, Vol. 37, No. 3, p. 562, 1990 (reference 5). However, as described in T. Kwok et al, Proceeding of the Seventh International IEEE VLSI Multilevel Interconnection Conference, p. 106, 1990 (reference 6), when the interface between different kinds of metals is provided in the current path, there is produced a discontinuity in the movement of carrier substances in the metal wiring, so that the electromigration reliability might be decreased to a large extent as compared with the metal wiring formed on a flat substrate. That is to say, when it is assumed that a current flows from the lower metal wiring to the upper metal wiring, the movement of aluminum atoms which is caused by an electron flow passing through the aluminum alloy film 107-1 in the upper metal wiring 107 is prevented by the interface between the aluminum alloy film 107-1 and the tungsten plug 108. Therefore, the aluminum atoms are stored in the upper metal wiring 107, so that a hillock 109 is formed in the upper metal wiring near the via hole 105. The hillock might produce a breakage of the TiW film 107-2 of the upper metal wiring 107. At the same time, a void 110 might be formed in the lower metal wiring 103 in the vicinity of the via hole 105 as shown in FIG. 3. This is due to the fact that aluminum atoms in the aluminum alloy film 103-2 in the lower metal wiring 103 are moved by the electron flow although the supply of aluminum atoms from the upper metal wiring 107 is prevented by the interface between the aluminum alloy film 107-1 and the W plug 108. These hillock 109 and void 110 might cause the shortcircuit and breakage of the interconnection between the lower and upper metal wirings 103 and 107 and might increase the resistance of the interconnection.
Similarly the interface between metals of different kinds produces the discontinuity in the movement of impurities such as Si and Cu added in the aluminum alloy film and the concentration of the impurity becomes non-uniform. For instance, in the above mentioned reference 5 there is described that the resistance of the via contact is increased by the discontinuity in the movement of Si atoms. Further in the reference 6, there is explained that when the concentration of Cu atoms is locally decreased at a portion near the via connection, the electromigration reliability might be decreased at such a portion.
As explained above, in LSI having the design rule smaller than about 0.5 .mu.m, the known multilevel interconnect structure shown in FIG. 1 could not be utilized, because the operation speed of the semiconductor device is limited due to the increase in the via contact resistance and the reliability of the device is decreased by the electromigration.
In U.S. Pat. No. 5,154,949 issued on Oct. 13, 1992 (reference 7) and corresponding EP Application 0 420 594 A2 published on Apr. 3, 1991 (reference 8), there is disclosed a method of depositing an aluminum film by CVD using alkyl aluminum hydrides. In FIGS. 4A to 4E of this reference, there are shown a process for forming source and drain electrodes for a field effect transistor. In U.S. Pat. No. 5,151,305 issued on Sep. 29, 1992 (reference 9), there is described another method, in which a first aluminum film is selectively formed by a selective Al-CVD using alkyl aluminum hydrides, and then a second aluminum film is formed on the first aluminum film by sputtering or CVD. However, these references do not state or suggest the formation of plugs in the multilevel interconnect structure.
Furthermore, in LSI a thickness of the interlayer insulating film is not uniform, but fluctuates over the whole surface. Then, a depth of via holes formed in such an interlayer insulating film varies in accordance with positions of the via holes. For instance, when a via hole is formed in a thick portion of the interlayer insulating film, a depth of this via hole becomes large. In this manner, there are formed a number of via holes having different thicknesses. Then, it would be difficult to form plugs such that the via holes are sufficiently filled with the plugs. That is to say, when the plugs are formed such that the deepest via hole is embedded with a plug, top portions of remaining plugs protrude the surface of the interlayer insulating film, and when the plugs are formed such that the most shallow via hole is just embedded with a plug, remaining via holes could not be fully filled with plugs. When the via holes are not sufficiently filled with the plugs, the via contact resistance is increased and the property of the semiconductor device is greatly decreased.